1. Field of the Invention
This invention relates to electronic circuit components, and particularly to variable analog delay line devices for analog signal processing on a single integrated circuit chip using a switched capacitor storage scheme.
2. State of the Art
A delay line in an electronic circuit functions to insert a time increment between a signal and a replicated version of that signal. Such a device finds application for signal processing in various contexts. Several varieties of delay lines are commercially available:
Active delay lines have inputs and outputs which are buffered with logic drivers, typically transistor-transistor logic (TTL) and emitter-coupled logic (ECL). Active delay lines are digital only; that is, they have no analog delay capability. Most companies which produce digital delay lines also provide "programmable" delay devices, whose chips have a 3-bit to 8-bit (usually 3 to 5-bit) input address for discretely variable delays up to the maximum. Typical maximum delay times for these devices range from 0.1 to 1000 ns. The delay-to-risetime ratio inherent to these devices is not meaningful, because their outputs are actively buffered. (Hence, the signal output risetime is a function of the digital buffer).
Passive, lumped constant, delay lines contain no active elements (such as logic drivers). They consist of inductive and capacitive components, which provide a fixed delay time. Usually, these devices include taps, which selectively provide a range of delay values up to a given maximum. Commercially available delay lines of this type offer maximum delay times ranging from 1 to 1000 ns, with delay-to-risetime ratios varying from 3 to 10 (most being between 3 and 6), and signal attenuations up to 12%. Apparently, the vendors of passive delay lines offer no "programmable" analog delay line. It is understood that to do so would require much more circuitry on the chip, because a linear driver would be required for each output port.
Cable delay lines comprise coaxial cables cut to specific lengths to provide fixed signal delays. Cable delay lines are characteristically expensive, heavy and large; they also tend to be quite dispersive for delays longer than 100 ns. "Programmable" cable delay lines are available, in which a binary sequence of cable lengths is switched into a total delay line, not exceeding 100 ns of total delay.
Trombone delay lines are basically wave guide cavities structured so that their lengths can be very accurately adjusted with a vernier. These devices provide very short but precise and adjustable delay times. Trombone delay lines are available having 2 ps timing resolution over 5 ns of delay, continuously variable with a mechanical knob or vernier.
Other types of delay lines include air dielectric tuned resonators, which are available for fixed delays at specified central frequencies. These resonators are used for RF applications, typically at .about.1 GHz, and are suitable for high power applications as well. "Non-dispersive" delay lines may be obtained for center frequencies of 30 to 1400 MHZ, with delays from 0.2 to 20 microseconds and bandwidths from 5 to 100 MHZ.
The great majority of existing analog delay devices are of the "lumped constant" design, which consist of "lumped" inductors and capacitors in a transmission line configuration. (For signal delays of less than one microsecond, the commercial delay lines are usually in chip form.) These devices offer poor delay-to-risetime ratios and all cause significant signal distortion and some degree of signal attenuation. When higher performance delay characteristics are required (less signal dispersion and attenuation), the only previously available recourse has been to rely upon cable delay lines. However, cable delay lines are extremely expensive, heavy, bulky, and often difficult to incorporate into an electronics system.
Several US patents disclose recent advances in delay line devices. U.S. Pat. No. 5,453,710 discloses a quasi-passive switched capacitor delay line including a predetermined number of passive switched capacitor delay stages and an amplifier. Each delay stage includes a first transistor having a control terminal for receiving a clock phase, an input terminal for receiving an input signal, and an output terminal, a second transistor having a control terminal for receiving a different clock phase, an input terminal connected to the output terminal of the first switching device, an output terminal coupled to the amplifier input, and a capacitor coupled between the output terminal of the first transistor and a common supply voltage.
According to U.S. Pat. No. 5,291,083, a "bucket brigade" analog delay line with voltage limiting feedback includes an input stage for receiving an input signal and a series of delay stages coupled to the input stage for propagating the input signal through the line. Each delay stage contains a storage capacitor for holding either a signal charge or a reference charge, a transfer device for transferring charge from one stage to another at regular clock intervals, and a tap circuit for allowing external sampling of the propagated input signal. Similarly, U.S. Pat. No. 4,771,196 discloses an electronically variable active analog delay line that utilizes cascaded differential transconductance amplifiers with integrating capacitors and negative feedback from the output to the input of each noninverting amplifier.
U.S. Pat. No. 4,999,799 discloses an apparatus for producing the Fourier coefficients of a time and/or space-varying input signal utilizing a bank of delay filters whose outputs are selectively connected to the inputs of a bank of accumulating circuits, each of which produces one of the desired Fourier coefficients.
U.S. Pat. No. 4,475,170 discloses a delay network including a plurality of signal sample and hold circuits selectively connected to an input bus to which the analog input signal is applied. Each sample and hold circuit is formed utilizing a storage capacitor and a source follower, thereby requiring less area on a semiconductor device surface than other sample and hold circuits which utilize operational amplifiers.